1. Field of the Invention
The present invention relates to an automatic gain control circuit, provided in a communication system or in an audio system, for controlling the gain of a variable gain amplifier circuit in accordance with the amplitude of an input signal.
2. Description of the Related Art
In a communication system, an audio system or the like, an automatic gain control (AGC) circuit for controlling the gain of an amplifier circuit in accordance with the amplitude of an input signal typically employs an integrator using a capacitor. The capacitor required in such an integrator, however, has a quite large capacitance value, and it is thus difficult to incorporate the capacitor into a semiconductor integrated circuit.
AGC circuits that do need to use capacitors and thus can be easily incorporated into semiconductor integrated circuits include one disclosed by the present inventors, for example (see, e.g., Patent Document 1). In the conventional AGC circuit, as shown in FIG. 21, for example, a rectifier 112 and a voltage comparator 113 generate a count control signal corresponding to the output of a variable gain amplifier block 111. The count control signal makes an up-down counter 114 count up or count down, and a digital-to-analog converter 115 and an amplifier 116 produce a gain control signal according to the count value of the up-down counter 114. FIG. 21 shows an example in which the AGC circuit is set so that as the count value of the up-down counter 114 becomes smaller, the gain of the variable gain amplifier block 111 is increased.
When the level of a signal input to the variable gain amplifier block 111 is raised to cause the output of the variable gain amplifier block 111 to exceed the level of a set threshold value Vth, the up-down counter 114 counts up to thereby reduce the gain of the variable gain amplifier block 111. On the other hand, when the output of the variable gain amplifier block 111 does not exceed the level of the set threshold value Vth, the up-down counter 114 does not count up but counts down to thereby increase the gain of the variable gain amplifier block 111.
[Patent Document 1] Japanese Laid-Open Publication No. 2004-274571
Nevertheless, the conventional AGC circuit has the following drawbacks. When a signal having a waveform shown in FIG. 22A is input, the up-down counter 114 counts up in a time period T3 in which the input signal level rises sharply. This causes the voltage of the gain control signal to be increased as shown in FIG. 22B, so that the gain of the variable gain amplifier block 111 is reduced so as to maintain the original signal level. Then, when the input signal level suddenly drops in a time period T4, the up-down counter 114 counts down to lower the voltage of the gain control signal, thereby increasing the gain of the variable gain amplifier block 111 so as to maintain the original signal level.
However, if the signal level is put back to the same level in an instant, discomfort in terms of audibility is caused because realism and perspective are lost. In general, it is desirable that an attack operation for lowering a high signal level be performed quickly, but if a recovery operation for putting a lowered signal level back to the original level is performed too quickly, discomfort increases. Thus, as shown in FIGS. 22C and 22D, the frequency of a downcount clock is set lower than that of an upcount clock so that the recovery operation is performed slowly.
In the conventional AGC circuit, however, when a signal having a waveform such as shown in FIG. 22A is input, the output signal changes as shown in FIG. 22E, in which the amplitude varies linearly during the recovery operation. In addition, when the recovery operation is completed and the amplitude becomes constant, the amplitude stops varying suddenly. This produces a problem in that great discomfort occurs in terms of audibility.